Verilog MCP Server
About
Generate Verilog testbenches, lint RTL code (7 rules), and scaffold UVM verification environments — directly inside Claude Code via MCP.
Details
- Author
- kaiwenyu147369
- Downloads
- 317
- Categories
- Developer Tools
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Setting up with Highlight
This MCP is not yet compatible with Highlight’s one-click setup. However, you can still use it with Highlight by following these steps:
- Download and install Highlight from highlightai.com/download
- Navigate to the plugins tab and select "Add Custom Plugin"
-
Configure the plugin with the settings below
Plugin Name
Verilog MCP ServerCommand (node, npx, python, etc.)Please refer to the README for specific instructions on how to obtain API keys or other required environment variables.
- Enable "Start Automatically" if you want the plugin to start when Highlight launches
From the repository
{
"mcpServers": {
"verilog-mcp-server": {
"command": "python",
"args": [
"server.py"
]
}
}
}
Claude Desktop / Cursor
Paste into your MCP client config file to install this server.
{
"mcpServers": {
"verilog mcp server": {
"verilog-mcp-server": {
"command": "python",
"args": [
"server.py"
]
}
}
}
}
McpServers
{
"verilog-mcp-server": {
"command": "python",
"args": [
"server.py"
]
}
}
Features
- generate_testbench — Paste a Verilog module, get a complete testbench with clock, reset sequence, DUT instantiation, and VCD dumping. - check_lint — 7 static RTL checks: missing reset, case-without-default, latch inference, width mismatch, blocking assignments in sequential blocks, non-blocking in combinational blocks, and multi-driver detection. - generate_uvm_env — Generate 10 UVM components (interface, transaction, sequence, driver, monitor, agent, scoreboard, environment, test, top) from a single DUT module.Tech
- Python MCP SDK 1.27.1 - stdio JSON-RPC - MIT license - 810+ linesLinks
- GitHub: https://github.com/kaiwenyu147369/verilog-mcp-serverSign in to leave a review
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